In recent years, the market scale of power semiconductors, such as IGBTs (Insulated gate bipolar transistors) and power MOSFETs, is expanding because of factors such as the electronization of control devices for automobiles, the proliferation of digital household appliances, and the use of inverter for energy consumption reduction of white goods. Researches are being conducted about the power semiconductors to improve their characteristics from the standpoint of energy consumption reduction. Especially, silicon carbide (hereinafter referred to as SiC) offers reduced on-state resistance because of its dielectric breakdown electric-field strength about ten times higher than that of silicon (hereinafter referred to as Si), and it also enables higher-temperature operations because of its large band width of 3 eV or more. Accordingly, the MOS (Metal-Oxide-Semiconductor) FETs using SiC are considered to be most promising as next-generation, high-voltage low-loss switching devices.
The MOS structure with Si is a well-known structure, but the structure using SiC has a problem of reduced channel mobility, because the oxide-semiconductor interface exhibits a larger interface state density when a thermal oxide film is used as the oxide. Accordingly, Patent Document 1 discloses a MOSFET structure manufactured by forming a drift layer on an SiC substrate, forming p-type base regions and n-type source regions by photolithography and ion implantation techniques, forming an n-type layer as a channel layer, and then forming a gate structure composed of a gate insulating film of, e.g. a thermal oxide, and a gate electrode. This makes it possible to reduce the influence of the oxide-semiconductor interface states on the carriers in the channel layer.
Also, the power semiconductors are required to perform normally-off operation in which no current flows between the source-drain when the gate voltage is zero, so as to ensure safe operation of the system. However, when an n-type layer is used as the channel layer as mentioned above, it is sometimes difficult to obtain normally-off conditions with good controllability. Accordingly, Patent Document 2 discloses a structure in which a normal p-type layer is operated in an inverted state (inversion MOS), and the document describes that the influence of the oxide-semiconductor interface states can be reduced by setting the concentration of the p-type region serving as the channel layer at 1×1016/cm3 or less.
Also, in order to achieve reduced on-state resistance and improved breakdown voltage which are indexes showing power device performance, it is effective to reduce device size and fabricate an increased number of devices per unit area. For this purpose, self-aligned manufacturing methods are proposed which are capable of accomplishing good controllability in forming the channel length determined by the dimensions of the p-type base region and n-type source region of the MOSFET. For example, Patent Document 3 discloses a method which uses a two-layered ion implantation mask and utilizes the spreading in ion implantation process so that a single implantation mask can be used instead of two independent implantation masks, and the dimensions can be controlled even when the channel length is as short as about 1 μm or less.
Patent Document 1: Japanese Patent Application Laid-Open No. 10-308510 (pp. 5-6, FIG. 1)
Patent Document 2: Japanese Patent Application Laid-Open No. 2000-150866 (pp 3-4, FIG. 1)
Patent Document 3: Japanese Patent Application Laid-Open No. 2004-363515 (p. 4, FIG. 1)